Carte Design for Testability, Debug and Reliability Sebastian Huhn

Design for Testability, Debug and Reliability

Next Generation Measures Using Formal Techniques

Limbă: engleză
Legare: Carte broșată
Disponibilitate: În depozitul extern
Expediem în 10-18 zile
420.02 lei
This book introduces several novel approaches to pave the way for the next generation of integrated...

Informații despre carte

Limbă
engleză
Legare
Carte - Carte broșată
Publicat
2022
Pagini
164
EAN
9783030692117
Enbook ID
38971551
Greutate
296
Dimensiuni
155 x 235 x 11

Descriere completă

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

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