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Carte Wafer-Level Integrated Systems Stuart K. Tewksbury

Wafer-Level Integrated Systems

Implementation Issues

Autor: Stuart K. Tewksbury
Limbă: engleză
Legare: Carte broșată
Editura: Springer-Verlag New York Inc.
Disponibilitate: În depozitul extern
Expediem în 5-8 zile
830.22 lei
From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices int...

Informații despre carte

Autor
Stuart K. Tewksbury
Limbă
engleză
Legare
Carte - Carte broșată
Publicat
2012
Pagini
456
EAN
9781461288985
ISBN
1461288983
Enbook ID
02179873
Editura
Springer-Verlag New York Inc.
Greutate
724
Dimensiuni
155 x 235 x 26

Descriere completă

From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.

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