Carte Power Integrity Techniques in Nanometer VLSI Design Jeffrey Fan

Power Integrity Techniques in Nanometer VLSI Design

A Technical Reference Book for Fabless IC Designers and VLSI Manufacturers in Academia and Industry

Autor: Jeffrey Fan
Limbă: engleză
Legare: Carte broșată
Disponibilitate: În depozitul extern
Expediem în 5-8 zile
282.73 lei
This book includes three major components in details: (1) Efficient algorithms to reduce the voltage...

Informații despre carte

Autor
Limbă
engleză
Legare
Carte - Carte broșată
Publicat
2010
Pagini
132
EAN
9783843381970
Enbook ID
06935803
Greutate
215
Dimensiuni
150 x 220 x 8

Descriere completă

This book includes three major components in details: (1) Efficient algorithms to reduce the voltage noise of on-chip power grid networks without considering process variations in traditional VLSI design are discussed. The algorithms are based on the Sequence of Linear Programming (SLP) as the optimization engine and a scheme through circuit partitioning to handle large-sized million nodes of circuit analysis. (2) A statistical model order reduction technique called Statistical Spectrum Model Order Reduction (SSMOR) is proposed to address the variation of nanometer VLSI fabrication. The analysis is based on the Hermite polynomial chaos representation of random processes. (3) Moreover, a stochastic method is proposed to analyze the variation of voltage drop in on-chip power grid networks considering lognormal leakage current variations with spatial correlations. A novel noise reduction technique for power grid networks in VLSI design is proposed in the presence of variational leakage current sources. The optimization engines are based on both sensitivity-based conjugate gradient method and sequence of linear programming approach.

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