Network Intrusion Detection Based on Shift-OR Circuit

Name: Network Intrusion Detection Based on Shift-OR Circuit
Brand: LAP Lambert Academic Publishing
SKU: 9783846591178
Price: 234.75 RON
Availability: InStock

A High Performance Circuit Design Applied to Network Intrusion Detection System on a SoPC Platform

Autor: Huang-Chun Roan

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Editura: LAP Lambert Academic Publishing

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This thesis introduces a novel FPGA based signature match co-processor that can serve as the core of...

Informații despre carte

Autor

Huang-Chun Roan

Limbă

engleză

Legare

Carte - Carte broșată

Publicat

2011

Pagini

EAN

9783846591178

Enbook ID

07065519

Editura

LAP Lambert Academic Publishing

Greutate

106

Dimensiuni

150 x 220 x 4

Descriere completă

This thesis introduces a novel FPGA based signature match co-processor that can serve as the core of a hardware-based network intrusion detection system (NIDS). The central idea of the signature match co-processor is an architecture based on the shift-or algorithm, which utilizes simple shift registers, OR gates, and ROMs where patterns are stored. Moreover, the architecture can be improved further by the removal of the ROM. The proposed architecture has been prototyped, simulated and synthesized by the Altera Stratix FPGA. Experimental results reveal that the circuit with processing two characters at a time attains the throughput up to 6.75 Gbits/sec with area cost of 0.7 logic elements (LEs) per character. The circuit with processing four input characters at a time achieves the throughput up to 9.2 Gbits/sec with area cost of 2.75 LE per character. As proposed architecture achieves higher throughput and less hardware resource in the FPGA implementations of NIDS.

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Network Intrusion Detection Based on Shift-OR Circuit

A High Performance Circuit Design Applied to Network Intrusion Detection System on a SoPC Platform

Informații despre carte

Descriere completă

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