Carte Logic Synthesis and Verification Algorithms Gary D. Hachtel

Logic Synthesis and Verification Algorithms

Limbă: engleză
Legare: Carte broșată
Disponibilitate: În depozitul extern
Expediem în 5-8 zile
457.84 lei
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthes...

Informații despre carte

Limbă
engleză
Legare
Carte - Carte broșată
Publicat
2013
Pagini
564
EAN
9781475770360
ISBN
1475770367
Enbook ID
02181673
Greutate
1126
Dimensiuni
178 x 254 x 33

Descriere completă

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. §Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. §A unique feature of this text is the large collection of solved problems. §Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

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