Logic Synthesis and Verification Algorithms

Name: Logic Synthesis and Verification Algorithms
Brand: Springer, Berlin
SKU: 9780387310046
Price: 433.99 RON
Availability: InStock

Autor: Gary D. Hachtel, Fabio Somenzi

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Legare: Carte broșată

Editura: Springer, Berlin

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433.99 lei

Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developm...

Informații despre carte

Autor

Gary D. Hachtel, Fabio Somenzi

Limbă

engleză

Legare

Carte - Carte broșată

Publicat

2006

Pagini

564

EAN

9780387310046

ISBN

0387310045

Enbook ID

01381693

Editura

Springer, Berlin

Greutate

928

Dimensiuni

155 x 235 x 30

Descriere completă

Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization.Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.Circuit designers and CAD tool developers alike will find Logic Synthesis and Verification Algorithms useful as an introductory and reference text. The rich collection of examples and solved problems make this book ideal for self study.Because of its careful balance of theory and application, Logic Synthesis and Verification Algorithms will serve well as a textbook for upper division and first year graduate students in electrical and computer engineering.

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