Estimation of Analog Layout Parasitics with Parameterized Polygons

Name: Estimation of Analog Layout Parasitics with Parameterized Polygons
Brand: LAP Lambert Academic Publishing
SKU: 9783838330303
Price: 282.85 RON
Availability: InStock

Algorithms for Partitioning Parameterized Polygons

Autor: I-Lun Tseng

Limbă:

Legare: Carte broșată

Editura: LAP Lambert Academic Publishing

Disponibilitate: În depozitul extern

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282.85 lei

Traditional analog integrated circuit design methodologies split circuit synthesis and physical layo...

Informații despre carte

Autor

I-Lun Tseng

Limbă

engleză

Legare

Carte - Carte broșată

Publicat

2009

Pagini

156

EAN

9783838330303

Enbook ID

07119465

Editura

LAP Lambert Academic Publishing

Greutate

249

Dimensiuni

150 x 220 x 9

Descriere completă

Traditional analog integrated circuit design methodologies split circuit synthesis and physical layout design into different phases. Since analog circuits are usually very sensitive, physical layout effects, such as parasitics, can have significant influence on the performance and even the functionality of the design. Lack of considering layout effects in the circuit synthesis phase can result in numerous re-design iterations. Developing new analog design flows, methodologies, and automation tools are thus required in order to solve the problem. This book describes a new analog circuit design flow which uses parameterized representation of physical layouts in order to estimate layout-induced parasitics. With the use of algorithms for partitioning parameterized polygons, accurate models of extracted circuits, which include models of parasitics, can be generated automatically and efficiently. As a result, values of layout-induced parasitics can be calculated or estimated on the fly in the circuit synthesis process. Re-design iterations can thus be minimized.

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Estimation of Analog Layout Parasitics with Parameterized Polygons

Algorithms for Partitioning Parameterized Polygons

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Descriere completă

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