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Will nanoelectronic devices continue to scale according to Moore s law? At this moment, there is no easy answer since gate scaling is rapidly emerging as a serious roadblock for the evolution of CMOS technology. Channel engineering based on high-mobility semiconductor materials (e.g. strained Si, alternative orientation substrates, Ge or III-V compounds) could help overcome the obstacles since they offer performance enhancement. There are several concerns though. Do we know how to make complex engineered substrates (e.g. Germanium-on-Insulator)? Which are the best interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? Can we process these materials in short channel transistors using flows, toolsets and know how similar to that in Si technology? How do these materials and devices behave at the nanoscale? The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any close to a viable Ge and III-V MOS technology.
