Practical Guide for SystemVerilog Assertions

Name: Practical Guide for SystemVerilog Assertions
Brand: Springer-Verlag New York Inc.
SKU: 9781489992796
Price: 829.14 RON
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Autor: Meyyappan Ramanathan

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Legare: Carte broșată

Editura: Springer-Verlag New York Inc.

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SystemVerilog language consists of three categories of features -- Design, Assertions and Testbench....

Informații despre carte

Autor

Meyyappan Ramanathan

Limbă

engleză

Legare

Carte - Carte broșată

Publicat

2014

Pagini

334

EAN

9781489992796

ISBN

9781489992796

Enbook ID

09165443

Editura

Springer-Verlag New York Inc.

Greutate

551

Dimensiuni

155 x 235 x 17

Descriere completă

SystemVerilog language consists of three categories of features -- Design, Assertions and Testbench. Assertions add a whole new dimension to the ASIC verification process. Engineers are used to writing testbenches in verilog that help verify their design. Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today. SystemVerilog assertions (SVA) is a declarative language. The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously. This provides the engineers a very strong tool to solve their verification problems. The language is still new and the thinking is very different from the user's perspective when compared to standard verilog language. There is not enough expertise or intellectual property available as of today in the field. While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems. This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.§

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Practical Guide for SystemVerilog Assertions

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